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Fix boot.S stack initialization order for aarch32

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Co-authored-by: jbltx <1284323+jbltx@users.noreply.github.com>
This commit is contained in:
copilot-swe-agent[bot]
2025-11-12 18:24:42 +00:00
co-authored by jbltx
parent 18b0a3a45d
commit b7272f8a96
1 changed files with 12 additions and 17 deletions
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src/aarch32/boot.S
+12 -17
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@@ -9,44 +9,39 @@ _start:
#ifndef BCM2835 // BCM2835 has a mono-core CPU
// send 3 out of 4 cores to halt (mono-core)
// Read Proc feature Register 0
// Read Multiprocessor Affinity Register
mrc p15, #0, r1, c0, c0, #5
and r1, r1, #3
cmp r1, #0
bne halt
#endif
// set the C stack starting at address _start and downwards
// the other side is used by the kernel itself
ldr r5, =_start
mov sp, r5
// setup Fast Interrupts Requests (FIQ)
// setup Fast Interrupts mode (FIQ) stack - mode 0x11
cps #0x11
ldr sp, =MEM_FIQ_STACK
// setup Interrupts Requests (IRQ)
// setup Interrupts mode (IRQ) stack - mode 0x12
cps #0x12
ldr sp, =MEM_IRQ_STACK
// setup Interrupts Requests (IRQ)
// setup Abort mode stack - mode 0x17
cps #0x17
ldr sp, =MEM_ABORT_STACK
// setup Abort mode
// setup Undefined mode stack - mode 0x1B
cps #0x1B
ldr sp, =MEM_ABORT_STACK
// setup SYstem mode
cps #0x1F
// setup SVC (Supervisor) mode - mode 0x13
// This is where we'll run the kernel
cps #0x13
ldr sp, =MEM_KERNEL_STACK
// set the C stack starting at address LOADADDR and downwards
// the other side is used by the kernel itself
ldr r5, =_start
mov sp, r5
// Enable Fast Interrupts
cpsie f
// TODO : invalidate data cache in L1
// TODO : vfpinit