first try

.gitignore

@@ -0,0 +1 @@
+/build/objects/*

build/Makefile

@@ -0,0 +1,43 @@
+CC = ../../../toolchain/bin/arm-none-eabi-gcc
+
+CPU = cortex-a7
+
+CFLAGS= -mcpu=$(CPU) -fpic -ffreestanding $(DIRECTIVES)
+CSRCFLAGS= -O2 -Wall -Wextra
+LFLAGS= -ffreestanding -O2 -nostdlib
+
+IMG_NAME=pb3000.img
+
+KER_SRC = ../src/kernel
+KER_HEAD = ../include
+COMMON_SRC = ../src/common
+OBJ_DIR = objects
+KERSOURCES = $(wildcard $(KER_SRC)/*.c)
+COMMONSOURCES = $(wildcard $(COMMON_SRC)/*.c)
+ASMSOURCES = $(wildcard $(KER_SRC)/*.s)
+OBJECTS = $(patsubst $(KER_SRC)/%.c, $(OBJ_DIR)/%.o, $(KERSOURCES))
+OBJECTS += $(patsubst $(COMMON_SRC)/%.c, $(OBJ_DIR)/%.o, $(COMMONSOURCES))
+OBJECTS += $(patsubst $(KER_SRC)/%.s, $(OBJ_DIR)/%.o, $(ASMSOURCES))
+HEADERS = $(wildcard $(KER_HEAD)/*.h)
+
+build: $(OBJECTS) $(HEADERS)
+	$(CC) -T linker.ld -o $(IMG_NAME) $(LFLAGS) $(OBJECTS)
+
+$(OBJ_DIR)/%.o: $(KER_SRC)/%.c
+	mkdir -p $(@D)
+	$(CC) $(CFLAGS) -I$(KER_SRC) -I$(KER_HEAD) -c $< -o $@ $(CSRCFLAGS)
+
+$(OBJ_DIR)/%.o: $(KER_SRC)/%.s
+	mkdir -p $(@D)
+	$(CC) $(CFLAGS) -I$(KER_SRC) -c $< -o $@
+
+$(OBJ_DIR)/%.o: $(COMMON_SRC)/%.c
+	mkdir -p $(@D)
+	$(CC) $(CFLAGS) -I$(KER_SRC) -I$(KER_HEAD) -c $< -o $@ $(CSRCFLAGS)
+
+run: build
+	qemu-system-arm -m 256 -M raspi2 -serial stdio -kernel $(IMG_NAME)
+
+clean:
+	rm -rf $(OBJ_DIR)
+	rm $(IMG_NAME)

build/linker.ld

@@ -0,0 +1,42 @@
+ENTRY(_start)
+ 
+SECTIONS
+{
+    /* Starts at LOADER_ADDR. */
+    . = 0x8000;
+    __start = .;
+    __text_start = .;
+    .text :
+    {
+        KEEP(*(.text.boot))
+        *(.text)
+    }
+    . = ALIGN(4096); /* align to page size */
+    __text_end = .;
+ 
+    __rodata_start = .;
+    .rodata :
+    {
+        *(.rodata)
+    }
+    . = ALIGN(4096); /* align to page size */
+    __rodata_end = .;
+ 
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+    }
+    . = ALIGN(4096); /* align to page size */
+    __data_end = .;
+ 
+    __bss_start = .;
+    .bss :
+    {
+        bss = .;
+        *(.bss)
+    }
+    . = ALIGN(4096); /* align to page size */
+    __bss_end = .;
+    __end = .;
+}

src/kernel/boot.s

@@ -0,0 +1,33 @@
+.section ".text.boot"
+
+.global _start
+
+_start:
+	mrc p15, #0, r1, c0, c0, #5
+	and r1, r1, #3
+	cmp r1, #0
+	bne halt
+
+	mov sp, #0x8000
+
+	ldr r4, =__bss_start
+	ldr r9, =__bss_end
+	mov r5, #0
+	mov r6, #0
+	mov r7, #0
+	mov r8, #0
+	b       2f
+
+1:
+	stmia r4!, {r5-r8}
+
+2:
+	cmp r4, r9
+	blo 1b
+
+	ldr r3, =kernel_main
+	blx r3
+
+halt:
+	wfe
+	b halt

src/kernel/kernel.c

@@ -0,0 +1,108 @@
+#include <stddef.h>
+#include <stdint.h>
+
+static inline void mmio_write(uint32_t reg, uint32_t data)
+{
+    *(volatile uint32_t*)reg = data;
+}
+
+static inline uint32_t mmio_read(uint32_t reg)
+{
+    return *(volatile uint32_t*)reg;
+}
+
+// Loop <delay> times in a way that the compiler won't optimize away
+static inline void delay(int32_t count)
+{
+    asm volatile("__delay_%=: subs %[count], %[count], #1; bne __delay_%=\n"
+            : "=r"(count): [count]"0"(count) : "cc");
+}
+
+enum
+{
+    // The GPIO registers base address.
+    GPIO_BASE = 0x3F200000, // for raspi2 & 3, 0x20200000 for raspi1
+
+    GPPUD = (GPIO_BASE + 0x94),
+    GPPUDCLK0 = (GPIO_BASE + 0x98),
+
+    // The base address for UART.
+    UART0_BASE = 0x3F201000, // for raspi2 & 3, 0x20201000 for raspi1
+
+    UART0_DR     = (UART0_BASE + 0x00),
+    UART0_RSRECR = (UART0_BASE + 0x04),
+    UART0_FR     = (UART0_BASE + 0x18),
+    UART0_ILPR   = (UART0_BASE + 0x20),
+    UART0_IBRD   = (UART0_BASE + 0x24),
+    UART0_FBRD   = (UART0_BASE + 0x28),
+    UART0_LCRH   = (UART0_BASE + 0x2C),
+    UART0_CR     = (UART0_BASE + 0x30),
+    UART0_IFLS   = (UART0_BASE + 0x34),
+    UART0_IMSC   = (UART0_BASE + 0x38),
+    UART0_RIS    = (UART0_BASE + 0x3C),
+    UART0_MIS    = (UART0_BASE + 0x40),
+    UART0_ICR    = (UART0_BASE + 0x44),
+    UART0_DMACR  = (UART0_BASE + 0x48),
+    UART0_ITCR   = (UART0_BASE + 0x80),
+    UART0_ITIP   = (UART0_BASE + 0x84),
+    UART0_ITOP   = (UART0_BASE + 0x88),
+    UART0_TDR    = (UART0_BASE + 0x8C),
+};
+
+void uart_init()
+{
+    mmio_write(UART0_CR, 0x00000000);
+
+    mmio_write(GPPUD, 0x00000000);
+    delay(150);
+
+    mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15));
+    delay(150);
+
+    mmio_write(GPPUDCLK0, 0x00000000);
+
+    mmio_write(UART0_ICR, 0x7FF);
+
+    mmio_write(UART0_IBRD, 1);
+    mmio_write(UART0_FBRD, 40);
+
+    mmio_write(UART0_LCRH, (1 << 4) | (1 << 5) | (1 << 6));
+
+    mmio_write(UART0_IMSC, (1 << 1) | (1 << 4) | (1 << 5) | (1 << 6) |
+            (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10));
+
+    mmio_write(UART0_CR, (1 << 0) | (1 << 8) | (1 << 9));
+}
+
+void uart_putc(unsigned char c)
+{
+    while ( mmio_read(UART0_FR) & (1 << 5) ) { }
+    mmio_write(UART0_DR, c);
+}
+
+unsigned char uart_getc()
+{
+    while ( mmio_read(UART0_FR) & (1 << 4) ) { }
+    return mmio_read(UART0_DR);
+}
+
+void uart_puts(const char* str)
+{
+    for (size_t i = 0; str[i] != '\0'; i ++)
+        uart_putc((unsigned char)str[i]);
+}
+
+void kernel_main(uint32_t r0, uint32_t r1, uint32_t atags)
+{
+    (void) r0;
+    (void) r1;
+    (void) atags;
+
+    uart_init();
+    uart_puts("Hello, kernel World!\r\n");
+
+    while (1) {
+        uart_putc(uart_getc());
+        uart_putc('\n');
+    }
+}